PCM1861 datasheet(80/145 Pages) TI2

80 / 145 page

PCM1860, PCM1861, PCM1862

PCM1863, PCM1864, PCM1865

SLAS831D – MARCH 2014 – REVISED MARCH 2018

www.ti.com

Product Folder Links: PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865

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11.4 Power-Up Sequence

The power-up sequence consists of the following steps:

1. Power-on reset

1. Power up AVDD, DVDD and IOVDD

2. Check if LDO is being driven with an external 1.8 V, or is an output. Enable LDO if required.

3. Release digital reset

2. Wait until analog voltage reference is stable

3. Configure clock (PLL requires < 250 µs)

4. Fade-in audio ADC content

11.5 Lowest Power-Down Modes

To achieve the lowest levels of power down and sleep current, the following recommended write sequences are

suggested on PCM186x software-controlled devices:

11.5.1 Lowest Power In Standby Mode (AVDD = DVDD = IOVDD = 3.3 V)

Consumption as low as 0.59 mW

0x00=0x00 //select page0

0x70=0x14 //power down reference

0x00=0x03 //select page3

0x12=0x41 //disable OSC

0x00=0x00 //select page0

11.5.2 Lowest Power in Sleep or Energysense Mode (AVDD = DVDD = IOVDD = 3.3 V)

Consumption as low as 14 mW

Clocks must be running during this process

0x00=0x00 //select page0

0x70=0x72 //enter in sleep mode

0x00=0xfd //select page253

0x14=0x10 //change global bias current

0x00=0x00 //select page0

Now stop the clocks

11.5.3 Lower Power in Sleep or Energysense Mode (AVDD = DVDD 3.3 V and IOVDD = 1.8 V)

Consumption as low as 11.15 mW

Clocks must be running during this process

0x00=0x00 //select page0

0x70=0x72 //enter in sleep mode

0x00=0xfd //select page253

0x14=0x10 //change global bias current

0x00=0x00 //select page0

stop the clocks (note: make sure the clock IO is 1.8 V)

PCM1861 Datasheet(PDF) 80 Page - Texas Instruments

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