PCM1861 datasheet(59/145 Pages) TI2

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BCK (fixed at 256 × fS)

LRCK / Frame Sync

24-Bit

No Gaps

50% Duty Cycle (Master Mode)

Ch1 data

(24 bits)

DATA

Ch2 data

(24 bits)

Ch3 data

(24 bits)

Ch4 data

(24 bits)

Ch5 data

(24 bits)

Ch6 data

(24 bits)

Ch7 data

(24 bits)

Ch8 data

(24 bits)

Ch9 data

(24 bits)

Ch10 data

(24 bits)

1BCK or 50% Duty Cycle (Slave Mode)

EMPTY

(16 bits)

Ch1 data

(24 bits)

LRCK / Frame Sync

BCK (fixed at 256 × fS)

LRCK / Frame Sync

24-Bit

8-Bit Gaps

50% Duty Cycle (Master Mode)

Ch1 data

(24 bits)

DATA

1BCK or 50% Duty Cycle (Slave Mode)

LRCK / Frame Sync

bits

Ch2 data

(24 bits)

Ch3 data

(24 bits)

Ch4 data

(24 bits)

Ch5 data

(24 bits)

Ch6 data

(24 bits)

Ch7 data

(24 bits)

Ch8 data

(24 bits)

Example

24-Bit

TDM Mode

Example

32-Bit

Mode

bits

PCM1860, PCM1861, PCM1862

PCM1863, PCM1864, PCM1865

www.ti.com

SLAS831D – MARCH 2014 – REVISED MARCH 2018

Product Folder Links: PCM1860 PCM1861 PCM1862 PCM1863 PCM1864 PCM1865

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In master mode, only a 50% duty cycle on the output is possible. This configuration is made by setting

TDM_LRCK_MODE (Page.0 0x0B) to 0.

Typically when interfacing to a DSP, only the rising edge on the first bit of data of the frame is required.

While the device is not transmitting data (but still being clocked), the DOUT pin will be Hi-Z (high impedance) to

allow other devices on the bus to transmit their data.

TDM mode is configured using I2S_FMT (Page.0 0x0B), TDM_LRCK_MODE (Page.0 0x0B), TDM_OSEL

(Page.0 0x0C)

The timing limits for the interface signals are defined by the Serial Audio Data Interface Configuration section

with the addition that the BCK period minimum must be at least 1 / (512 × fS) to make sure that data is clocked in

correctly.

The audio format is shown in Figure 46. The 24-bit data can fit up to 10 channels of data in a 256x bitclock

stream; however, the I2C-controlled devices only have two possible I2C addresses. The eight channels of audio

data should be no issue.

Figure 46. Audio Format for TDM

NOTE

TDM mode can only function up to 96 kHz sampling rate when IOVDD is 1.8 V. This is

due to an I/O limitation of 25 MHz at 1.8 V.

9.3.16.5 Decimation Filter Select

The PCM186x offers a choice of two different digital filters, a Classic FIR response and a low latency IIR.

9.3.16.6 Serial Audio Data Interface Configuration

The PCM186x devices interface to the audio system through LRCK, BCK and DOUT.

The PCM186x hardware-controlled devices are configured using pin MD4 to select between left-justified data and

I2S.

The PCM186x software-controlled devices are configured using register I2S_FMT (Page.0 0x0B). Use register

I2S_TX_OFFSET (Page.0 0x0D) when dealing with TDM systems to offset the data transmit.

In addition, the offset required for receiving 24-bit data is programmed using RX_TDM_OFFSET (P0, R0x0E).

PCM1861 Datasheet(PDF) 59 Page - Texas Instruments

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