PCM5121 datasheet(47/121 Pages) TI2

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PCM5121, PCM5122

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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018

Product Folder Links: PCM5121 PCM5122

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8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)

The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source

reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency

electromagnetic interference.

In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.

In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly

while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically

generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate

master clock. Table 33 describes the minimum and maximum BCK per LRCK for the integrated PLL to

automatically generate an internal SCK.

In software mode, the user must set all the PLL registers and clock divider registers for referencing BCK. See the

Clock Generation Using the PLL section for more information.

Table 33. BCK Rates (MHz) by LRCK Sample Rate for

PCM512x PLL Operation

SAMPLE F (kHz)

BCK (fS)

–

1.024

2.048

44.1

1.4112

2.8224

1.536

3.072

6.144

192

6.144

12.288

384

12.288

24.576

8.3.6.4 Clock Generation Using the PLL

The PCM512x supports a wide range of options to generate the required clocks for the DAC section as well as

interface and other control blocks as shown in Figure 63.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming BCK or SCK. In

software mode, a GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on Page

0, Register 13, D(6:4). The PCM512x provides several programmable clock dividers to achieve a variety of

sampling rates for the DAC and clocks for the NCP, OSR, and the audio processor. OSRCK for OSR must be

set at 16 fS frequency by DOSR on Page0, Register 30, D(6:0). See Figure 63.

If PLL functionality is not required, set the PLLEN value on Page 0, Register 4, D(0) to 0. In this situation, an

external SCK is required.

Table 34. PLL Configuration Registers

CLOCK MULTIPLEXER

FUNCTION

BITS

SRCREF

PLL reference

Page 0, Register 13, D(6:4)

DIVIDER

FUNCTION

BITS

DDSP

audio processor clock divider

Page 0, Register 27, D(6:0)

DACCK

DAC clock divider

Page 0, Register 28, D(6:0)

CPCK

NCP clock divider

Page 0, Register 29, D(6:0)

OSRCK

OSR clock divider

Page 0, Register 30, D(6:0)

DBCK

External BCK Div

Page 0, Register 32, D(6:0)

DLRK

External LRCK Div

Page 0, Register 33, D(7:0)

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