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PCM5121 Datasheet(PDF) 76 Page - Texas Instruments |
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PCM5121 Datasheet(HTML) 76 Page - Texas Instruments |
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76 / 121 page  76 PCM5121, PCM5122 SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018 www.ti.com Product Folder Links: PCM5121 PCM5122 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated 1: Master mode BCK clock divider is functional RLRK Master Mode LRCK Divider Reset This bit, when set to 0, will reset the BCK divider to generate LRCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. Default value: 0 0: Master mode LRCK clock divider is reset 1: Master mode LRCK clock divider is functional Table 64. Page 0 / Register 13 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 13 0D RSV SREF2 SREF1 SREF0 RSV RSV RSV RSV Reset Value 0 0 0 RSV Reserved Reserved. Do not access. SREF[2:0] PLL Reference This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode. Default value: 000 000: The PLL reference clock is SCK 001: The PLL reference clock is BCK 010: Reserved 011: The PLL reference clock is GPIO (selected using Page 0 / Register 18) others: Reserved (PLL reference is muted) SREF PLL Reference Default value: 0 Table 65. Page 0 / Register 14 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 14 0E RSV SDAC2 SDAC1 SDAC0 RSV RSV RSV RSV Reset Value 0 0 0 RSV Reserved Reserved. Do not access. SDAC[2:0] DAC clock source These bits select the source clock for DAC clock divider. Default value: 000 This Register requires use of the Clock Flex Register 000: Master clock (PLL/SCK and OSC auto-select) 001: PLL clock 010: Reserved 011: SCK clock 100: BCK clock others: Reserved (muted) Table 66. Page 0 / Register 18 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 18 12 RSV RSV RSV RSV RSV GREF2 GREF1 GREF0 Reset Value 0 0 0 |
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