PCM5121 datasheet(67/121 Pages) TI2

67 / 121 page

PCM5121, PCM5122

www.ti.com

SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018

Product Folder Links: PCM5121 PCM5122

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12 Register Maps

12.1 PCM512x Register Map

In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255

for next read or write command.

Table 49. Register Map Overview

NUMBER

DESCRIPTION

Page 0

Page select register

Analog control register

Standby, Powerdown requests

Mute

PLL Lock Flag, PLL enable

Reserved

SPI MISO function select

De-emphasis enable, SDOUT select

GPIO enables

BCK, LRCLK configuration

DSP GPIO Input

Reserved

Master mode BCK, LRCLK reset

PLL clock source select

14 - 19

Reserved

20 - 24

PLL dividers

25, 26

Reserved

DSP clock divider

DAC clock divider

NCP clock divider

OSR clock divider

Reserved

32, 33

Master mode dividers

fS speed mode

35, 36

IDAC (number of DSP clock cycles available in

one audio frame)

Ignore various errors

38,39

Reserved

40, 41

I2S configuration

DAC data path

DSP program selection

Clock missing detection period

Table 49. Register Map Overview (continued)

NUMBER

DESCRIPTION

Auto mute time

60 - 64

Digital volume

Auto mute

75 - 79

Reserved

80 - 85

GPIOn output selection

86, 87

GPIO control

88, 89

Reserved

DSP overflow

91 - 94

Sample rate status

95 - 107

Reserved

108

Analog mute monitor

109 - 118

Reserved

119

GPIO input

120

Auto Mute flags

121

Reserved

Page 1

Output amplitude type

Analog gain control

3, 4

Reserved

Undervoltage protection

Analog mute control

Analog gain boost

8, 9

VCOM configuration

Page 44

Coefficient memory (CRAM) control

Pages 44 - 52

Coefficient buffer - A (256 coeffs x 24 bits) : See

Table 51

Pages 62 - 70

Coefficient buffer - B (256 coeffs x 24 bits) : See

Table 52

71 - 252

Reserved

Page 253

63, 64

Clock Flex Mode

Pages 254 -

255

Reserved

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