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PCM5121 Datasheet(PDF) 94 Page - Texas Instruments |
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PCM5121 Datasheet(HTML) 94 Page - Texas Instruments |
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94 / 121 page  94 PCM5121, PCM5122 SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018 www.ti.com Product Folder Links: PCM5121 PCM5122 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated 011: 32-48 kHz 100: 88.2-96 kHz 101: 176.4-192 kHz 110: 384 kHz DTSR[3:0] Detected SCK Ratio (Read Only) These bits indicate the currently detected SCK ratio. Note that even if the SCK ratio is not indicated as error, clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the SCK ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The absolute SCK frequency must also be lower than 50 MHz. 0000: Ratio error (The SCK ratio is not allowed) 0001: SCK = 32 FS 0010: SCK = 48 FS 0011: SCK = 64 FS 0100: SCK = 128 FS 0101: SCK = 192 FS 0110: SCK = 256 FS 0111: SCK = 384 FS 1000: SCK = 512 FS 1001: SCK = 768 FS 1010: SCK = 1024 FS 1011: SCK = 1152 FS 1100: SCK = 1536 FS 1101: SCK = 2048 FS 1110: SCK = 3072 FS Table 105. Page 0 / Register 92 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 92 5C RSV RSV RSV RSV RSV RSV RSV DTBR8 Reset Value Table 106. Page 0 / Register 93 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 93 5D DTBR7 DTBR6 DTBR5 DTBR4 DTBR3 DTBR2 DTBR1 DTBR0 Reset Value RSV Reserved Reserved. Do not access. DTBR[8:0] Detected BCK Ratio (MSB) (Read Only) These bits indicate the currently detected BCK ratio, that is, the number of BCK clocks in one audio frame. Note that for extreme case of BCK = 1 FS (which is not usable anyway), the detected ratio will be unreliable. Table 107. Page 0 / Register 94 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 94 5E RSV CDST PLL-L LrckBck fS-SCKr SCKval BCKval fSval Reset Value RSV Reserved Reserved. Do not access. CDST Clock Detector Status (Read Only) This bit indicates whether the SCK clock is present or not. 0: SCK is present |
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