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PCM5121 Datasheet(PDF) 57 Page - Texas Instruments

Part # PCM5121
Description  PCM512x 2-VRMS DirectPath™, 112-dB and 106-dB Audio Stereo DACs With 32-Bit, 384-kHz PCM Interface
PDF  121 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

PCM5121 Datasheet(HTML) 57 Page - Texas Instruments

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PCM5121, PCM5122
www.ti.com
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
Product Folder Links: PCM5121 PCM5122
Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Table 44. I2C Bus Timing
MIN
MAX
UNIT
fSCL
SCL clock frequency
Standard
100
kHz
Fast
400
kHz
tBUF
Bus free time between a STOP and START condition
Standard
4.7
µs
Fast
1.3
tLOW
Low period of the SCL clock
Standard
4.7
µs
Fast
1.3
tHI
High period of the SCL clock
Standard
4.0
µs
Fast
600
ns
tRS-SU
Setup time for (repeated)START condition
Standard
4.7
µs
Fast
600
ns
tS-HD
Hold time for (repeated)START condition
Standard
4.0
µs
tRS-HD
Fast
600
ns
tD-SU
Data setup time
Standard
250
ns
Fast
100
tD-HD
Data hold time
Standard
0
900
ns
Fast
0
900
tSCL-R
Rise time of SCL signal
Standard
20 + 0.1CB
1000
ns
Fast
20 + 0.1CB
300
tSCL-R1
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit
Standard
20 + 0.1CB
1000
ns
Fast
20 + 0.1CB
300
tSCL-F
Fall time of SCL signal
Standard
20 + 0.1CB
1000
ns
Fast
20 + 0.1CB
300
tSDA-R
Rise time of SDA signal
Standard
20 + 0.1CB
1000
ns
Fast
20 + 0.1CB
300
tSDA-F
Fall time of SDA signal
Standard
20 + 0.1CB
1000
ns
Fast
20 + 0.1CB
300
tP-SU
Setup time for STOP condition
Standard
4.0
µs
Fast
600
ns
CB
Capacitive load for SDA and SCL line
400
pF
tSP
Pulse width of spike suppressed
Fast
50
ns
VNH
Noise margin at High level for each connected device (including hysteresis)
0.2 × VDD
V
8.4.2 VREF and VCOM Modes
See Choosing Between VREF and VCOM Modes for information on configuring these modes.
8.5 Programming
In software mode, the PCM512x can act as an I2S master, generating BCK and LRCK as outputs from the SCK
input.
Table 45. I2S Master Mode Registers
REGISTER
FUNCTION
Page0, Register 9, D(0), D(4), and D(5)
I2S Master mode select
Register 32, D(6:0)
BCK divider and LRCK divider
Register 33, D(7:0)



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