PCM5121 datasheet(48/121 Pages) TI2

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PLLCKIN

J.D

PLLCK

PLLCKIN

PLLCK

PCM5121, PCM5122

SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018

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Product Folder Links: PCM5121 PCM5122

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8.3.6.5 PLL Calculation

The PCM512x has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the

audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the

PLL allows operation from a wide variety of clocks that may be available in the system. The PLL input (PLLCKIN)

supports clock frequencies from 1 MHz to 50 MHz and is register programmable to enable generation of required

sampling rates with fine precision.

The PLL is enabled by default. The PLL can be turned on by writing to Page 0, Register 4, D(0). When the PLL

is enabled, the PLL output clock PLLCK is given by Equation 3.

where

•

R = 1, 2, 3,4, ... , 15, 16

•

J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999

•

K = [J value].[D value]

•

P = 1, 2, 3, ... 15

(3)

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while

D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

8.3.6.5.1

Examples:

•

If K = 8.5, then J = 8, D = 5000

•

If K = 7.12, then J = 7, D = 1200

•

If K = 14.03, then J = 14, D = 0300

•

If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

•

1 MHz

≤ ( PLLCKIN / P ) ≤ 20 MHz

•

64 MHz

≤ (PLLCKIN x K x R / P ) ≤ 100 MHz (in VREF mode)

•

72 MHz

≤ (PLLCKIN x K x R / P ) ≤ 86 MHz (in VCOM mode)

•

≤ J ≤ 63

When the PLL is enabled and D

≠ 0000, the following conditions must be satisfied:

•

6.667 MHz

≤ PLLCLKIN / P ≤ 20 MHz

•

64 MHz

≤ (PLLCKIN x K x R / P ) ≤ 100 MHz (in VREF mode)

•

72 MHz

≤ (PLLCK IN x K x R / P ) ≤ 86 MHz (in VCOM mode)

•

≤ J ≤ 11

•

R = 1

When the PLL is enabled,

•

fS = (PLLCLKIN × K × R) / (2048 × P)

•

The value of N is selected so that fS × N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and fS = 44.1 kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 35.

8.3.6.5.1.1

Recommended PLL Settings

Recommended values for the PLL can be found after the register descriptions in this data sheet. Different values

are defined based on the device configuration for VREF or VCOM mode.

Other configurations are possible, at your own risk.

PCM5121 Datasheet(PDF) 48 Page - Texas Instruments

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