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PCM5121 Datasheet(PDF) 52 Page - Texas Instruments

Part # PCM5121
Description  PCM512x 2-VRMS DirectPath™, 112-dB and 106-dB Audio Stereo DACs With 32-Bit, 384-kHz PCM Interface
PDF  121 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

PCM5121 Datasheet(HTML) 52 Page - Texas Instruments

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A6
A5
A4
A3
A2
A1
A0
W
D6
D5
D4
D3
D2
D1
D0
D7
MS
MC
MOSI
MISO
HI-Z
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
D7
D6
D5
D4
D3
D2
D1
D0
Register Index (or Address)
Register Data
MSB
LSB
R/W
52
PCM5121, PCM5122
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
www.ti.com
Product Folder Links: PCM5121 PCM5122
Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Device Functional Modes (continued)
MC is the serial bit clock, used to shift data in and out of the control port by falling edge of MC, and MS is the
mode control enable with LOW active, used to enable the internal mode register access. If feedback from the
device is not required, the MISO pin can be assigned to GPIO1 by register control.
8.4.1.1.1.1
Register Read and Write Operation
All read/write operations for the serial control port use 16-bit data words. Figure 66 shows the control data word
format. The most significant bit is the read/write bit. For write operations, the bit must be set to 0. For read
operations, the bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or
address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written
to, or the data that was read from, the register specified by IDX[6:0].
Figure 66 and Figure 67 show the functional timing diagram to write or read through the serial control port. MS is
held at a logic-1 state until a register access. To start the register write or read cycle, set MS to logic 0. Sixteen
clocks are then provided on MC, corresponding to the 16 bits of the control data word on MOSI and read-back
data on MISO. After the eighth clock cycle has completed, the data from the indexed-mode control register
appears on MISO during the read operation. After the sixteenth clock cycle has completed, the data is latched
into the indexed-mode control register during the write operation. To write or read subsequent data, MS is set to
logic 1 once (see tMHH in Figure 71).
Figure 66. Control Data Word Format; MDI
NOTE
B8 is used for selection of Write or Read. Setting = 0 indicates a Write, while = 1 indicates
a Read. Bits 15–9 are used for register address. Bits 7–0 are used for register data.
Multiple-byte write or read (up to 8 bytes) is supported while MS is kept low. The address
field becomes the initial address, automatically incrementing for each byte.
Figure 67. Serial Control Format; Write, Single Byte



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