TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
USB CONTROLLER
Preliminary
9-11
OUT CSR1 Register (OCSR1n)
0x80000550
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CTGL
STST
ISST
FLFF
DERR OVER
FFL
ORDY
This register maintains the status information of endpoints.
CTGL [7]
Type
Data Toggle Bit
1
W
The data toggle sequence bit is reset to DATA0.
STST [6]
Type
STALL Handshake Issued
1
R
Indicates that the OUT token is ended with a STALL
handshake. USB issues a stall handshake to the host if
host sends more than MAXP data for the OUT token.
0
W
Clear STST flag by writing 0.
ISST [5]
Type
Issue STALL Handshake
1
Issue a STALL Handshake to the USB.
0
R/W
End the STALL condition.
FLFF [4]
Type
Issue FIFO Flush
1
OUT FIFO is flushed.
This bit can be set only when the ORDY flag is set.
0
R/W
Stop flushing FIFO.
DERR [3]
Type
Data Error
1
R
Valid only in ISO mode. This bit should be sampled with
ORDY (Bit[0]). “1” indicates the data packet due to be
unloaded by the CPU has an error (either bit stuffing or
CRC). If two packets are loaded into the FIFO, and the
second packet has an error, then this bit gets set only after
the first packet is unloaded. This bit is automatically
cleared when ORDY gets cleared.
OVER [2]
Type
OUT FIFO Over Run
1
R
Valid only in ISO mode. This bit is set if the core is not
able to load an OUT ISO token into the FIFO. Cleared
by writing 0.
FFL [1]
Type
OUT FIFO Full
1
R
Indicates that no more packets can be accepted
ORDY [0]
Type
OUT Packet Ready
1
R
Indicates the USB has loaded a packet of data into the FIFO.
0
W
Clears ORDY flag by writing 0.
Once the CPU reads the FIFO for the entire packet, this bit
should be cleared. (refer ACLR bit of OCSR2n register)
*) FFL == 0 && ORDY == 0 : Indicates that there is no packet in the FIFO.
FFL == 0 && ORDY == 1 : Indicates that there is 1 packet in the FIFO.
FFL == 1 && ORDY == 1 : Indicates that there are 2 packets in the FIFO.
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