TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
USB CONTROLLER
Preliminary
9-12
OUT CSR2 Register (OCSR2n)
0x80000554
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ACLR
ISO
Reserved
This register maintains the configuration of endpoints.
ACLR [7]
Type
Auto Clear
1
Enable Auto Clear.
Whenever the CPU reads data from the OUT FIFO, ORDY
will automatically be cleared by the USB.
0
R/W
Disable Auto Clear. (Default)
Once the CPU reads the FIFO for the entire packet, ORDY
should be cleared manually.
ISO [6]
Type
ISO/BULK Mode Select
0
R/W
Configures endpoint mode as BULK. (Default)
1
R/W
Configures endpoint mode as ISO.
OUT FIFO Write Count 1 Register (OFIFO1n)
0x80000558
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
OFIFO1n
OUT FIFO Write Count 2 Register (OFIFO2n)
0x8000055C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
OFIFO2n
There are two registers, OFIFO1n and OFIFO2n, which maintain the write count.
OFIFO1n maintains the lower bytes, while OFIFO2n maintains the higher byte.
Write count = OFIFO2n * 256 + OFIFO1n
When ORDY bit of OCSR1n is set for OUT endpoints, these registers maintain the
number of bytes in the packet due to be read by the CPU.
EP0 FIFO Register (EP0FIFO)
0x80000580
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
FIFO
EP1 FIFO Register (EP1FIFO)
0x80000584
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
FIFO
EP2 FIFO Register (EP2FIFO)
0x80000588
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
FIFO
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