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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CAMERA INTERFACE
Preliminary
18-2
Figure 18.2 shows the packing method.
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8
pixel clock
HS
Y[7:0]
CbCr[7:0]
LSB
MSB
0
31
LSB
MSB
0
31
Y0
Y1
Y2
Y3
Cb0
Cb2
Cb4
Cb6
Cr0
Cr2
Cr4
Cr6
Packing at separating each channel
Y0 Cb0
Y1 Cr0
Y2
Y3
Y4
Y5
Cb2
Cr2
Cb4
Cr4
Unpacking at separating each
channel
Figure 18.2 Packing Method
The CIF asserts interrupt signal after each frame image has been stored to memory.
18.2 Related Blocks
To enable CIF (Camera Interface), CIFEN bit of MISCFG register (0x80000A1C)
must be set to “1”. CIFEN bit enables Camera Interface signals on to the GPIO pins
listed in the table below. CIFEN has a precedence over GPIO control bits.
Table 18.1 CIF Signal Mapping
Camera Interface Signals
GPIO Pins
HS
GPIO_D[17]
VS
GPIO_D[16]
CAMCLK
GPIO_D[15]
Data[7:4]
GPIO_D[21:18]
Data[3:0]
GPIO_A[3:0]
At power on reset, CIFEN is disabled and the CIF signals are treated as normal GPIO.
After the signals are enabled, CIFCLK (the main clock of CIF) must be enabled and
configured to the proper frequency. Refer to section “CLOCK GENERATOR” for
CIFCLK related descriptions.
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