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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
I2C CONTROLLER
Preliminary
17-2
After the signals are enabled, I2CCLK (the main clock of I2C) must be enabled and configured to the proper
frequency. Refer to section “CLOCK GENERATOR” for I2CCLK (EX2CLK) related descriptions.
For internal synchronization, the APB clock frequency must be faster than the I2CCLK frequency.
fI2CLK ≤ fHCLK / 4.0
17.3 Register Description
Table 17.2 I2C Register Map (Base Address = 0x80000800)
Name
Address
Type
Reset
Description
PRES
0x00
R/W
0xFFFF
Clock Prescale register
CTRL
0x04
R/W
0x0000
Control Register
TXR
0x08
W
0x0000
Transmit Register
CMD
0x0C
W
0x0000
Command Register
RXR
0x10
R
0x0000
Receive Register
SR
0x14
R
0x0000
Status Register
Prescale Register (PRES)
0x80000800
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Clock Prescale data
This register is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a
5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change
the value of the prescale register only when ‘EN’ bit is cleared.
Example :
CLK Input frequency = 8MHz , Desired SCL frequency = 100KHz
Prescale = ( 8MHz / (5*100KHz) ) – 1 = 15
Control Register (CTR)
0x80000804
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
EN
IEN MOD
RESERVED
EN [7]
I2C Core enable bit
0
Disabled
1
Enabled
IEN [6]
I2C Core interrupt enable bit
0
Disabled
1
Enabled
MOD [5]
I2C Data Width
0
8bit Mode
1
16bit Mode
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