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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
I2C CONTROLLER
Preliminary
17-1
17 I2C CONTROLLER
17.1 Functional Description
Byte
Command
Controller
DataI/O
Shift
Register
Clock
Generator
Bit
Command
Controller
Prescale
Register
Command
Register
Status
Register
Transmit
Register
Receive
Register
SCL
SDA
I2CCLK from Clock Controller
Figure 17.1 I2C Block Diagram
17.2 Related Blocks
Before enable the I2C Controller, CFGI2C[1:0] of MISCFG register (0x80000A1C) must be set according to the
external connection. CFGI2C[1:0] enables I2C signals on to the GPIO pins as listed in the table below. CFGI2C has
a priority over GPIO control bits. Note that GPIO_D[17:16] is also shared with CIF (Camera Interface) signals.
When CIFEN is set, GPIO_D[17:16] will be assigned to CIF signals regardless of CFGI2C value.
Table 17.1 I2C Signal Mapping
CIFEN
CFGI2C[1:0]
SCL
SDA
X
00
Disabled
Disabled
X
01
GPIO_A[9]
GPIO_A[8]
X
10
GPIO_A[11]
GPIO_A[10]
0
11
GPIO_D[17]
GPIO_D[16]
1
11
Disabled
Disabled
At power on reset, CFGI2C is disabled and the I2C signals are treated as normal GPIO. GPIO_A[9:8] are used
as Bus Width Configuration bits (BW[1:0]) at power on reset. Due to this functionality, I2C signals may not be
selected. Refer to section “MEMORY CONTROLLER” for BW[1:0] description. (MCFG register)
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