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TCC76 Datasheet(PDF) 208 Page - List of Unclassifed Manufacturers

Part # TCC76
Description  32-bit RISC Microprocessor For Digital Media Player
PDF  259 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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TCC76 Datasheet(HTML) 208 Page - List of Unclassifed Manufacturers

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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
ECC (ERROR CORRECTION CODE)
Preliminary
16-2
16.2 Register Description
Table 16.1 ECC Register Map (Base Address = 0x80000900)
Name
Address
Type
Reset
Description
ECC_CTRL
0x00
R/W
0x00000000
ECC Control Register
ECC_BASE
0x04
R/W
0x00000000
Base Address for ECC Calculation
ECC_MASK
0x08
R/W
0x00000000
Address mask for ECC area.
ECC_CLR
0x0C
W
-
Clear ECC output register
SLC_ECC0
0x10
R
0x00000000
1st Block ECC output for SLC NAND
SLC_ECC1
0x14
R
0x00000000
2nd Block ECC output for SLC NAND
SLC_ECC2
0x18
R
0x00000000
3rd Block ECC output for SLC NAND
SLC_ECC3
0x1C
R
0x00000000
4th Block ECC output for SLC NAND
SLC_ECC4
0x20
R
0x00000000
5th Block ECC output for SLC NAND
SLC_ECC5
0x24
R
0x00000000
6th Block ECC output for SLC NAND
SLC_ECC6
0x28
R
0x00000000
7th Block ECC output for SLC NAND
SLC_ECC7
0x2C
R
0x00000000
8th Block ECC output for SLC NAND
MLC_ECC0W
0x40
W
-
MLC NAND ECC calculation register 0
MLC_ECC1W
0x44
W
-
MLC NAND ECC calculation register 1
MLC_ECC0R
0x48
R/W
0x00000000
Calculated ECC output 0 for MLC NAND
MLC_ECC1R
0x4C
R/W
0x00000000
Calculated ECC output 1 for MLC NAND
ECC Control Register (ECC_CTRL)
0x80000900
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
ECC_CNT[8:4]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ECC_CNT[3:0]
MLC_STAT[3:0]
HLD
0
EC0
ME
SLC_CNT[2:0]
SE
ECC_CNT [20:12]
ECC Word Counter
N
Means that N number of words are calculated
MLC_STAT [11:8]
Represent Internal State for MLC
1000
0100
0010
0001
ST_ECC : Compare state. It compares two ECC for error-checking.
ST_WR : Write state. It calculates ECC for write cycle.
ST_RD : Read state. It calculates ECC for read cycle.
ST_IDLE : Idle state. It waits until there is access for MLC device.
HLD
[7]
ECC Hold
1
Hold Enabled. ECC output register is not changed.
EC0
[5]
ECC Zero
1
Means that ECC output register (MLC_ECC0R & MLC_ECC1R
for MLC, SLC_ECC0 & SLC_ECC1 for SLC) contains 0.
ME
[4]
MLC ECC Enable
1
Enable ECC for MLC
0
Disable ECC of MLC



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