
TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
ECC (ERROR CORRECTION CODE)
Preliminary
16-3
SLC_CNT
[3:1]
ECC Block Count
N (0 ~ 7)
Means that N number of ECC block (256 bytes) are calculated.
This is useful to determine how many ECC output registers are
valid. That is, N number of ECC output register counting from
SLC_ECC0 are valid.
SE
[0]
SLC ECC Enable
1
Enable ECC for SLC
0
Disable ECC of SLC
ECC Base Address Register (ECC_BASE)
0x80000904
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ECC_BASE[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ECC_BASE[15:0]
ECC Address Mask Register (ECC_MASK)
0x80000908
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ECC_MASK[9:0]
0
The ECC is calculated whenever the specified region of memory is accessed. The region
for ECC calculating is determined by ECC_BASE & ECC_MASK register. The real base
address is determined by following formula.
Real base address = ECC_BASE(0x80000904) & ~(ECC_MASK[9:0] << 2)
(The real base address is assumed to be word aligned, so the least 2 bits are always 0.)
The size of region is also determined by ECC_MASK register. If ECC_MASK register
have N concatenated 0 from LSB, the region size is set to 2N bytes.
ECC Clear Register (ECC_CLR)
0x8000090C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Don’t care
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Don’t care
Whenever this register is written by any value, all ECC output registers are cleared to 0.
ECC Output Register for SLC (SLC_ECCx)
0x80000910 + x*4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
SLC_ECCx_0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SLC_ECCx_1
SLC_ECCx_2
These registers contain ECC output for SLC. It calculates ECC of SSFDC standard, and
can contain up to 8 block of data. Every time it finishes calculating ECC for each
block, it shifts the ECC values for previous block from SLC_ECC0 upward to
SLC_ECC7 register. So the ECC for last block is always stored at SLC_ECC0
register.
For each output register, there are a total of 22 bits of parity data (6 bits for column parity