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SLRC400 Datasheet(PDF) 123 Page - NXP Semiconductors |
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SLRC400 Datasheet(HTML) 123 Page - NXP Semiconductors |
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123 / 130 page  Philips Semiconductors Product Specification Rev. 2.0 November 2001 I •CODE Reader IC SL RC400 123 Preliminary 19.5.2.3 Bus Timing for EPP SYMBOL PARAMETER MIN MAX UNIT tLLLH nAStrb pulse width 20 ns tAVLH Multiplexed Address Bus valid to nAStrb high (Set Up Time) 15 ns tLHAX Multiplexed Address Bus valid after nAStrb high (Hold Time) 8 ns tCLSL NCS low to nDStrb low 0 ns tSHCH nDStrb high to NCS high 0 ns tSLDV,R nDStrb low to DATA valid (read cycle) 65 ns tSHDZ nDStrb low to DATA high impedance (read cycle) 20 ns tSLDV,W nDStrb low to DATA valid (write cycle, Set up Time) 35 ns tSHDX DATA hold after nDStrb high (write cycle, Hold Time) 8 ns tSHRX nWrite hold after nDStrb high 8 ns tSLSH nDStrb pulse width 65 ns tRVSL nWrite valid to nDStrb low 8 ns tSLWH nDStrb low to nWait high 75 ns tSHWL nDStrb high to nWait low 75 ns Table 19-12: Timing Specification for Common Read/Write Strobe Remark: The figure does not distinguish between the Address Write Cycle and a Data Write Cycle. Take in account, that timings for the Address Write and Data Write Cycle different. For the EPP-Mode the address lines A0 to A2 have to be connected as described in 4.3. NCS t CLSL t SHDX t SHDZ D0 ... D7 D0 ... D7 A0 ... A7 t SLDV,R t SLDV,W nDStrb nAStrb t SLSH nWrite nWait t SLWH t SHWL t RVSL t SHRX t SHCH Figure 19-3: Timing Diagram for Common Read/Write Strobe |
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