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SLRC400 Datasheet(PDF) 121 Page - NXP Semiconductors |
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SLRC400 Datasheet(HTML) 121 Page - NXP Semiconductors |
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121 / 130 page  Philips Semiconductors Product Specification Rev. 2.0 November 2001 I •CODE Reader IC SL RC400 121 Preliminary 19.5.2 AC OPERATING SPECIFICATION 19.5.2.1 Bus Timing for Separated Read/Write Strobe SYMBOL PARAMETER MIN MAX UNIT tLHLL ALE pulse width 20 ns tAVLL Multiplexed Address Bus valid to ALE low (Address Set Up Time) 15 ns tLLAX Multiplexed Address Bus valid after ALE low (Address Hold Time) 8 ns tLLWL ALE low to NWR, NRD low 15 ns tCLWL NCS low to NRD, NWR low 0 ns tWHCH NRD, NWR high to NCS high 0 ns tRLDV NRD low to DATA valid 65 ns tRHDZ NRD high to DATA high impedance 20 ns tWLDV NWR low to DATA valid 35 ns tWHDX DATA hold after NWR high (Data Hold Time) 8 ns tWLWH NRD, NWR pulse width 65 ns tAVWL Separated Address Bus valid to NRD, NWR low (Set Up Time) 30 ns tWHAX Separated Address Bus valid after NWR high (Hold Time) 8 ns tWHWL period between sequenced read / write accesses 150 ns Table 19-10: Timing Specification for Separated Read/Write Strobe Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3. t AVLL ALE t LHLL NCS t CLWL t WHDX t RHDZ D0 ... D7 D0 ... D7 t WLDV t RLDV t LLAX t WHWL NWR NRD t WLWH t LLWL t WHWL A0 ... A2 t AVWL Multiplexed Addressbus A0 ... A2 t WHAX Separated Addressbus A0 ... A2 t WHCH Figure 19-1: Timing Diagram for Separated Read/Write Strobe |
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