ISOTMP35RDFPR datasheet(28/44 Pages) TI2

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8.2 Layout

8.2.1 Layout Guidelines

Proper PCB layout is critical to achieving the full performance of the ISOTMP35R device. Place the device as

close as possible to the heat source to minimize thermal gradients and improve measurement accuracy. The

TSENSE pins must be positioned to provide direct thermal coupling to the heat-generating element.

If the heat source is located on the opposite side of the PCB, implement a small copper area directly beneath

the TSENSE pins and connect the copper area to the heat source using thermal vias. This copper region act as

a local thermal interface, while the vias provide a low thermal resistance path between the heat source and the

sensor. Use multiple vias in close proximity to improve heat transfer.

Place all filtering components, including bypass capacitors and RC filters, as close as possible to the device pins

to minimize parasitic inductance and reduce susceptibility to electromagnetic interference (EMI).

Signal routing must be carefully managed. The VOUT trace must be routed away from high dv/dt switching nodes

and high-current paths, and trace length must be minimized to reduce noise pickup. When long routing distances

are required, additional filtering or buffering is recommended to maintain signal integrity (see Section 8.1.2 for

more details).

A low-impedance ground connection is required. A continuous ground plane provides a stable reference and

reduces noise coupling.

The isolation barrier requires a minimum creepage and clearance distance of 8mm. A minimum of a 2-layer

PCB stackup is recommended. In 4-layer PCB designs, signal routing can be implemented on either the top

or bottom layers. The region beneath the isolation barrier must remain free of conductive elements, including

copper planes, traces, pads, and vias, to maintain the isolation integrity of the device.

See Figure 8-5 for an example of the required keep-out region beneath the device.

Keep this space free

from planes, traces,

pads and vias

10 mils

Figure 8-5. Isolation Barrier Keep-Out Region (Cross-Section View)

8.2.2 Layout Example

Keep space beneath

device free of any planes,

traces, pads and vias

VDD

VOUT

GND

ISOTMP35R

Heat

High Voltage Heat Source

To ADC Input

To GND Plane

To VDD Plane

Bypass

Capacitor

Load

Capacitor

To GND Plane

Isolation

Resistor

Figure 8-6. ISOTMP35R Layout Example

ISOTMP35R

SNIS244A – SEPTEMBER 2025 – REVISED MAY 2026

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