RZSLASHG3S datasheet(3/88 Pages) RENESAS

3 / 88 page

RZ/G3S Group

1. Overview

R01DS0489EJ0120

Rev.1.20

Page 3 of 88

May 29, 2026

1.1.2

CPU Peripheral

Item

Description

Clock Pulse Generator

(CPG)

● Generates the clocks from external clock (EXCLK 24 MHz).

Maximum Arm Cortex-A55 clock: 1.1 GHz

Maximum Arm Cortex-M33 clock: 250 MHz

Maximum DDR clock: 800 MHz (DDR4-1600 / LPDDR4-1600)

Maximum AXI-bus clock: 200 MHz

Maximum APB-bus clock: 100 MHz

● SSC (Spread Spectrum Clock) supported

Direct Memory Access Controller

(DMAC)

● 2 modules, 16 channels per module

● Transfer request: On-chip peripheral request / auto request (software trigger)

● A specific DMA transfer interval can be specified to adjust the bus occupancy.

● LINK mode (DMA transfer under descriptor control) supported

● Transfer information can be automatically reloaded

Interrupt Controller

● Arm® CoreLink™ Generic Interrupt Controller (GIC-600) for Arm Cortex-A55

● Nested Vectored Interrupt Controller (NVIC) for Arm Cortex-M33

● External Interrupt pins (NMI, IRQ7 to IRQ0, TINT31-0)

● On-chip peripheral Interrupts: Priority level set for each module

Message Handling Unit

(MHU)

● Message handling function between Arm Cortex-A55 and Arm Cortex-M33

● Assert interrupt to inform message and response from/to Arm Cortex-A55, Cortex-M33

General-purpose I/O

(GPIO)

● General-purpose I/O ports

Thermal Sensor Unit

(TSU)

● 1 channel

1.1.3

Internal Memory

Item

Description

On-chip RAM

● RAM of 1 Mbytes (ECC)

RZ/G3S Datasheet(PDF) 3 Page - Renesas Technology Corp

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