RZSLASHG3S datasheet(28/88 Pages) RENESAS

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RZ/G3S Group

3. Electrical Characteristics

R01DS0489EJ0120

Rev.1.20

Page 28 of 88

May 29, 2026

3.5

AC Characteristics

Conditions:

VBATT_VDD = 1.50 to 1.95 V, VDD = PLL16/23/4_AVDD = 0.905 to 0.99 V,

PVDD33 = 3.0 to 3.6 V, PVDD18 = ADC_AVDD18 = OTP_AVDD18 = 1.65 to 1.95 V,

JTAG_PVDD = 1.65 to 1.95 V, XSPI_PVDD = 1.65 to 1.95 V / 3.0 to 3.6 V,

I3C_PVDD = 1.1 to 1.3 V / 1.65 to 1.95 V, VDD_ISO = PCIE_VDD09 = 0.905 to 0.99 V,

SDn_PVDD (n = 0, 1) = 1.65 to 1.95 V / 3.0 to 3.6 V,

PVDD182533_n (n = 0, 1) = 1.65 to 1.95 V / 2.3 to 2.7 V / 3.0 to 3.6 V,

USB_VDD33 = 3.0 to 3.6 V, USB_AVDD18 = USB_VDD18 = PCIE_VDD18 = 1.65 to 1.95 V,

DDR_VAA = 1.65 to 1.95 V, DDR_VDDQ = 1.06 to 1.17 V (LPDDR4) / 1.14 to 1.26 V (DDR4),

USB_VSS = 0 V, VSS = 0 V, Ta

= −40 to +85℃, T

= −40 to +125℃

3.5.1

Clock Timing

Table 3.13

Clock Timing Table

Item

Symbol

Min.

Max.

Unit

Figures

XIN clock input frequency

fEX

24 – 50ppm*1

24 + 50ppm*1

MHz

Figure 3.6

XIN clock input cycle time

tEXcyc

41.67

AUDIO_CLK1, AUDIO_CLK2 clock input frequency

(external clock is input)

fEX

MHz

AUDIO_CLK1, AUDIO_CLK2 clock input cycle time

(external clock is input)

tEXcyc

100

XIN, AUDIO_CLK1, AUDIO_CLK2

clock input low level pulse width

tEXL

0.4

0.6

tEXcyc

XIN, AUDIO_CLK1, AUDIO_CLK2

clock input high level pulse width

tEXH

0.4

0.6

tEXcyc

XIN, AUDIO_CLK1, AUDIO_CLK2

clock input rise time

tEXr

—

XIN, AUDIO_CLK1, AUDIO_CLK2

clock input fall time

tEXf

—

Oscillator stabilization time

tOSC

—

Figure 3.7,

Figure 3.8

Mode hold time

tMDH

—

µs

Mode setup time

tMDS

—

µs

Note 1.

When using RGMII interface. If not using RGMII mode, this spec is ±100 ppm.

1/2 PVDD

XIN,

AUDIO_CLK1,

AUDIO_CLK2

(input)

tEXcyc

tEXH

tEXL

VIH

VIL

VIH

1/2 PVDD

tEXf

tEXr

Note:

When the clock is input on the EXCLK, AUDIO_CLK1 or AUDIO_CLK2

Figure 3.6

EXCLK, AUDIO_CLK1 and AUDIO_CLK2 Clock Input Timing

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