RZSLASHG3S datasheet(21/88 Pages) RENESAS

21 / 88 page

RZ/G3S Group

3. Electrical Characteristics

R01DS0489EJ0120

Rev.1.20

Page 21 of 88

May 29, 2026

(*1)

(*2)

(*3)

(*2)

VBATT

0.9V

1.8V

1.1V/1.2V

PRST#

1.5V

1.8V/3.3V

1.2V

3.3V

0.9V

USB_VDD18

USB_AVDD18

PCIE_VDD18

USB_VDD33

1.8V

PVDD18

OTP_AVDD18

ADC_AVDD18

SD0/1_PVDD

ETHER0/1_PVDD

1.8V/3.3V

2.5V

DDR_VDDQ

VBATT_VDD

1.8V

DDR_VAA

VBATTRESET#

VDD_ISO

PCIE_VDD09

G10

ALL_ON

High

(*7)

< 100msec (Max)

> 2msec (Min)

(*6)

(*4)

(*5)

PVDD33, JTAG_PVDD

XSPI_PVDD(1.8/3.3V)

I3C_PVDD(1.2/1.8V)

VDD,

PLL16/23/4_AVDD

Note 1.

G3 must be powered off before G2, G5 and powered on after G2, G5. G3 and G7 can be powered on/off at the same time.

Note 2.

G4, G6 must be powered off before G3 and powered on after G3.

Note 3.

G8 must be powered off before G7 and powered on after G7.

Note 4.

It is recommended that all the power domains are powered on or off within approximately 100 msec.

Note 5.

PRST# must be High after 2 msec from VDD (G2) power on.

Note 6.

PRST# must be changed to Low before powered off.

Note 7.

G5 must be powered off before G2 and powered on after G2.

Figure 3.4

Power-On/Power-Off Sequence 4 (ALL_ON to VBATT, VBATT to ALL_ON)

RZ/G3S Datasheet(PDF) 21 Page - Renesas Technology Corp

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