RZSLASHG3S datasheet(2/88 Pages) RENESAS

2 / 88 page

RZ/G3S Group

1. Overview

R01DS0489EJ0120

Rev.1.20

Page 2 of 88

May 29, 2026

Overview

1.1

Outline of Specification

1.1.1

CPU Core

Item

Description

System CPU Cortex-A55

● Arm Cortex-A55 Single Core 1.1 GHz

● L1 I-cache: 32 Kbytes (Parity) / D-cache : 32 Kbytes (ECC)

● L2 cache: Not included

● L3 cache: 256 Kbytes (ECC)

● NEON™ / FPU supported

● Cryptographic Extension supported

● Arm® v8.2-A architecture

System CPU Cortex-M33

● Arm Cortex-M33 Processor 250 MHz × 2 cores

● Security Extension supported

● Floating Extension supported*1

● Arm® v8-M architecture

Boot

● Bootable CPU: Cortex-A55, Cortex-M33*4

● Boot device:

Boot Mode 0:

Booting from eSD

Boot Mode 1:

Booting from eMMC

Boot Mode 2:

Booting from a serial flash memory (Single / Quad /Octal)*3

Boot Mode 3:

Booting from SCIF download

● Boot device voltage: 1.8 V*2, 3.3 V

Debug Interface

● Arm® CoreSight™ architecture

● JTAG / SWD interface supported

● ETF 16 Kbytes for program flow trace (each cluster)

● JTAG Disable supported

Note 1.

One core supports Floating Extension

Note 2.

1.8 V is supported in booting from eMMC and serial flash memory.

Note 3.

A serial flash memory (Octal) is supported when Boot device voltage is 1.8 V.

Note 4.

Cortex-M33 booting is supported from a serial flash memory and SCIF download.

RZ/G3S Datasheet(PDF) 2 Page - Renesas Technology Corp

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