RZSLASHG3S datasheet(7/88 Pages) RENESAS

7 / 88 page

RZ/G3S Group

1. Overview

R01DS0489EJ0120

Rev.1.20

Page 7 of 88

May 29, 2026

1.1.7

Timer

Item

Description

Multi-function Timer Pulse Unit 3

(MTU3a)

● 9 channels (16 bits × 8 channels, 32 bits × 1 channel)

● Module clock frequency: 100 MHz

● Maximum 28 lines of pulse inputs/outputs and 3 lines of pulse inputs

● 14 types of count clocks selectable

● Input capture function

● 39 outputs compare and input capture registers

● Counter clear operation (Simultaneous counter clearing by Compare match or Input capture is

available)

● Simultaneous writing to multiple timer counters (TCNT)

● Synchronous input/output of each register due to synchronous operation of the counter

● Buffered operation

● Cascade-connected operation

● 43 types of interrupt sources

● Automatic transfer of register data

● Pulse output modes

Toggle, PWM, complementary PWM, and reset-synchronized PWM modes

● Synchronization of multiple counters

● Phase counting mode

– 16-bit mode (channel 1 and 2)

– 32-bit mode (channel 1 and 2)

● Counter function of dead time compensation

● Digital filter functions for the input capture and external count clock pin

Port Output Enable 3

(POE3)

● Control of the high-impedance state of the MTU3a waveform output pins

● Activation with four input pins

● Activation on detection of short-circuited outputs (detection of simultaneous PWM output to the

active level)

● Activation by register write

● Additional programming of output control target pins is possible.

General PWM Timer

(GPT)

● 32 bits × 8 channels

● Counting up or down (sawtooth wave), counting up and down (triangular wave) selectable for

all channels

● Independent selectable for each channel

● 2 input/output pins per channel

● 2 output compare / input capture registers per channel

● For the 2 output compare / input capture registers of each channel, 4 registers are provided as

buffer registers and are capable of operating as comparison registers when buffering is not in

use

● In output compare operation, buffer switching can be at peaks or troughs, enabling the

generation of laterally asymmetrically PWM waveforms

● Registers for setting up frame intervals on each channel (with capability for generating

interrupts on overflow or underflow)

● Generation of dead times in PWM operation

● Synchronous start / stop / clear of counters on arbitrary channels

● Starting, stopping, and clearing up/down counters in response to a maximum of eight events

● Starting, stopping, and clearing up/down counters in response to input level comparison

● Starting, stopping, and clearing up/down counters in response to a maximum of four external

triggers

● Output pin invalidation functions due to dead time error or detection of short circuit between

output pins

● Digital filter functions for the input capture and external trigger pins

Port Output Enable for GPT

(POEG)

● Output prohibition control of the GPT waveform output pin

● Activation with up to four input pins

● Activation by dead time error detection or output short detection

● Activation by register write

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