RZSLASHG3S datasheet(35/88 Pages) RENESAS

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RZ/G3S Group

3. Electrical Characteristics

R01DS0489EJ0120

Rev.1.20

Page 35 of 88

May 29, 2026

3.5.4.2

eMMC Host Interface Timing (HS-SDR)

Table 3.19

eMMC Host Interface Timing (MMC HS-SDR 3.3-V Power Supply)

Item

Symbol

Min.

Max.

Unit

Figures

SD0_CLK clock cycle

tMMCPP

32.00

—

Figure 3.14

SD0_CLK clock high level width

tMMCWH

13.50

—

SD0_CLK clock low level width

tMMCWL

13.50

—

SD0_CLK clock rise time

tMMCLH

—

SD0_CLK clock fall time

tMMCHL

—

SD0_CMD/SDDAT output delay

tMMCODLY

−4.50

4.0

SD0_CMD/SDDAT input set up time

tMMCISU

5.5

—

SD0_CMD/SDDAT input hold time

tMMCIH

2.0

—

SD0_CMD/SDDAT input data width

tMMCIDW

—

Table 3.20

eMMC Host Interface Timing (MMC HS-SDR 1.8-V Power Supply)

Item

Symbol

Min.

Max.

Unit

Figures

SD0_CLK clock cycle

tMMCPP

20.00

—

Figure 3.14

SD0_CLK clock high level width

tMMCWH

9.25

—

SD0_CLK clock low level width

tMMCWL

9.25

—

SD0_CLK clock rise time

tMMCLH

—

2.45

SD0_CLK clock fall time

tMMCHL

—

2.45

SD0_CMD/SDDAT output delay

tMMCODLY

−2.00

2.50

SD0_CMD/SDDAT input set up time

tMMCISU

5.00

—

SD0_CMD/SDDAT input hold time

tMMCIH

1.40

—

SD0_CMD/SDDAT input data width

tMMCIDW

—

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