RZSLASHG3S datasheet(9/88 Pages) RENESAS

9 / 88 page

RZ/G3S Group

1. Overview

R01DS0489EJ0120

Rev.1.20

Page 9 of 88

May 29, 2026

1.1.8

Peripheral Module

Item

Description

I2C Bus Interface

(I2C)

● 4 channels (ch0,1 = Dedicated pin, ch2,3 = Multiplexed pin)

● Master mode and slave mode supported

● Support for 7-bit and 10-bit slave address formats

● Support for multi-master operation

● Timeout detection

I3C Bus Interface

(I3C)

● 1 channel

● Master (Main Master/Secondary Master) mode and Slave mode selectable

● SDR (I3C Single Data Rate) Mode

– Private Message

– Broadcast Message (Common Command Code)

– Direct Message (Common Command Code)

● Legacy I2C Message

– Fast-mode (Fm): Up to 400 kbit/s

– Fast-mode Plus (Fm+): Up to 1 Mbit/s

● Slave Interrupt Request

● Master Ship Request (Secondary Master only)

● Support for 7-bit slave address formats

● Synchronous Timing Control

– Sync Mode: Synchronous Basic Mode

● Asynchronous Timing Control

– Async Mode 0: Asynchronous Basic Mode

– Async Mode 1: Asynchronous Advanced Mode

● Error Detection

Serial Communication Interface

with FIFO (SCIFA)

● 6 channels

● Clock synchronous mode or asynchronous mode selectable

● Simultaneous transmission and reception (full-duplex communication) supported

● Dedicated baud rate generator

● Separate 16-byte FIFO registers for transmission and reception

● Modem control function (channel 0, 1 and 2 in asynchronous mode)

Serial Communication Interface

(SCIg)

● 2 channels

● Clock synchronous mode, asynchronous mode, or smart card interface mode is selectable

● Simultaneous transmission and reception (full-duplex communication) supported

● Dedicated baud rate generator

● LSB first / MSB first selectable

● Modem control function

● Encoding and decoding of IrDA communications waveforms in accord with version 1.0 of the

IrDA standard (on channel 0)

Renesas Serial Peripheral

Interface (RSPI)

● 5 channels

● SPI operation

● Master mode and slave mode supported

● Programmable bit length, clock polarity, clock phase can be selected

● Consecutive transfers

● LSB first / MSB first selectable

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