RZSLASHG3S datasheet(60/88 Pages) RENESAS

60 / 88 page

RZ/G3S Group

3. Electrical Characteristics

R01DS0489EJ0120

Rev.1.20

Page 60 of 88

May 29, 2026

Table 3.39

I3C Push-Pull Timing Parameters for SDR Mode

Item

Symbol

Min.

Typ.

Max.

Unit

Figures

Notes

SCL Clock Frequency

fSCL

0.01

12.5

12.9

MHz

—

SCL Clock Low Period

tLOW

—

Figure 3.45

—

tDIG_L

—

Figure 3.46

*2, *4

SCL Clock High Period for Mixed Bus

tHIGH_MIXED

—

Figure 3.46

—

tDIG_H_MIXED

—

Figure 3.46

*2, *3

SCL Clock High Period

tHIGH

—

Figure 3.45

—

tDIG_H

—

Figure 3.46

Figure 3.45

Clock in to Data Out for Slave

tSCO

—

Figure 3.51

*7, *8

SCL Clock Rise Time

tCR

—

150e06 × 1 /

fSCL (capped

at 60)

Figure 3.45

SCL Clock Fall Time

tCF

—

150e06 × 1 /

fSCL (capped

at 60)

Figure 3.45

SDA Signal Data Hold in

Push-Pull Mode

Master

tHD_PP

tCR + 3 and

tCF +3

—

Figure 3.50

*4, *6

Slave

tHD_PP

—

Figure 3.52

SDA Signal Data Setup in Push-Pull

Mode

tSU_PP

—

N/A

Figure 3.50,

Figure 3.51

—

Clock After Repeated START (Sr)

tCASr

tCASmin

—

N/A

Figure 3.53

—

Clock Before Repeated START (Sr)

tCBSr

tCASmin / 2

—

N/A

Figure 3.53

—

Capacitive Load per Bus Line

(SDA/SDL)

—

Note 1.

FSCL = 1 / (tDIG_L + tDIG_H)

Note 2.

tDIG_L and tDIG_H are the clock low and high periods as seen at the receiver end of the I3C bus using VIL and VIH (see Figure

3.45).

Note 3.

When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure

that I2C Devices do not interpret I3C signaling as valid I2C signaling.

Note 4.

As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks, and

tCR + 3 for rising edge clocks.

Note 5.

The clock maximum rise/fall time is capped at 60 ns. For lower frequency rise and fall the maximum value is limited at 60 ns,

and is not dependent upon the clock frequency.

Note 6.

tHD_PP is a Hold time parameter for Push-Pull Mode that has a different value for Master mode vs. Slave mode. In SDR Mode

the Hold time parameter is referred to as tHD_SDR.

Note 7.

Devices with more than 12 ns of tSCO delay shall set the limitation bit in the BCR, and shall support the GETMXDS CCC to

allow the Master to read this value and adjust computations accordingly. For purposes of system design and test

conformance, this parameter should be considered together with pad delay, bus capacitance, propagation delay, and clock

triggering points.

Note 8.

Pad delay based on 90Ω/4 mA driver and 50 pF load. Note that Master may be a Slave in a multi-Master system, and thus

shall also adhere to this requirement.

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