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HD64F36034 Datasheet(PDF) 116 Page - Renesas Technology Corp

Part # HD64F36034
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
PDF  592 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F36034 Datasheet(HTML) 116 Page - Renesas Technology Corp

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Section 6 Power-Down Modes
Rev. 4.00 Mar. 15, 2006 Page 84 of 556
REJ09B0026-0400
Function
Active Mode
Sleep Mode
Subactive
Mode
Subsleep
Mode
Standby Mode
Timer V
Functioning
Functioning
Reset
Reset
Reset
Watchdog
timer
Functioning
Functioning
Retained (functioning if the internal oscillator are
selected as a count clock*)
Peripheral
functions
SCI3, SCI3_2*
2
Functioning
Functioning
Reset
Reset
Reset
TinyCAN
Functioning
Functioning
Retained
Retained
Retained
SSU
Functioning
Functioning
Retained
Retained
Retained
Subtimer
Functioning
Functioning
Functioning
Functioning
Retained
(functioning if
the on-chip
oscillator is
enabled)
Timer B1
Functioning
Functioning
Retained*
Retained
Retained
Timer Z
Functioning
Functioning
Retained (When internal clock
φ is selected as a
count clock, the counter counts up with sub
clock*.)
A/D converter
Functioning
Functioning
Reset
Reset
Reset
Note:
*
Registers can be read from or written to in subactive mode.
6.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a
transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to
subactive mode when the bit is 1.
When the
RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
6.2.2
Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop
functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, on-
chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.



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