HD64F36034 datasheet(112/592 Pages) RENESAS

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Section 6 Power-Down Modes

Rev. 4.00 Mar. 15, 2006 Page 80 of 556

REJ09B0026-0400

Bit

Bit Name

Initial

Value

R/W

Description

SA1

SA0

R/W

Subactive Mode Clock Select 1 and 0

These bits select the operating clock frequency in

subactive and subsleep modes. The operating clock

frequency changes to the set frequency after the SLEEP

instruction is executed.

00:

W/8

01:

W/4

1X:

W/2

[Legend]

X: Don't care.

6.1.3

Module Standby Control Register 1 (MSTCR1)

MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.

Bit

Bit Name

Initial

Value

R/W

Description

7, 6



All 0



Reserved

These bits are always read as 0.

MSTS3

R/W

SCI3 Module Standby

The SCI3 enters standby mode when this bit is set to 1.

MSTAD

R/W

A/D Converter Module Standby

The A/D converter enters standby mode when this bit is

set to 1.

MSTWD

R/W

Watchdog Timer Module Standby

The watchdog timer enters standby mode when this bit is

set to 1. When the internal oscillator is selected for the

watchdog timer clock, the watchdog timer operates

regardless of the setting of this bit.



Reserved

This bit is always read as 0.

MSTTV

R/W

Timer V Module Standby

The timer V enters standby mode when this bit is set to 1.



Reserved

This bit is always read as 0.

HD64F36034 Datasheet(PDF) 112 Page - Renesas Technology Corp

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