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HD64F36034 Datasheet(PDF) 253 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 253 Page - Renesas Technology Corp |
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253 / 592 page  Section 12 Timer Z Rev. 4.00 Mar. 15, 2006 Page 221 of 556 REJ09B0026-0400 12.4.8 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 12.8 shows the register combinations used in buffer operation. Table 12.8 Register Combinations in Buffer Operation General Register Buffer Register GRA GRC GRB GRD When GR is Output Compare Register: When a compare match occurs, the value in the buffer register of the corresponding channel is transferred to the general register. This operation is illustrated in figure 12.35. Buffer register Comparator TCNT General register Compare match signal Figure 12.35 Compare Match Buffer Operation When GR is Input Capture Register: When an input capture occurs, the value in TCNT is transferred to the general register and the value previously stored in the general register is transferred to the buffer register. This operation is illustrated in figure 12.36. TCNT Buffer register General register Input capture signal Figure 12.36 Input Capture Buffer Operation |
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