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HD64F36034 Datasheet(PDF) 254 Page - Renesas Technology Corp |
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HD64F36034 Datasheet(HTML) 254 Page - Renesas Technology Corp |
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254 / 592 page ![]() Section 12 Timer Z Rev. 4.00 Mar. 15, 2006 Page 222 of 556 REJ09B0026-0400 Complementary PWM Mode: When the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general register. Here, the value of the buffer register is transferred to the general register in the following timing: 1. When TCNT_0 and GRA_0 are compared and their contents match 2. When TCNT_1 underflows Reset Synchronous PWM Mode: The value of the buffer register is transferred from compare match A0 to the general register. Example of Buffer Operation Setting Procedure: Figure 12.37 shows an example of the buffer operation setting procedure. [1] Designate GR as an input capture register or output compare register by means of TIOR. [2] Designate GR for buffer operation with bits BFD1, BFC1, BFD0, or BFC0 in TMDR. [3] Set the STR bit in TSTR to 1 to start the count operation of TCNT. [1] [2] [3] Select GR function Set buffer operation Start count operation Buffer operation <Buffer operation> Figure 12.37 Example of Buffer Operation Setting Procedure |
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