HD64F36034 datasheet(255/592 Pages) RENESAS

Part #	HD64F36034

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

PDF	592 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Timer Z

Rev. 4.00 Mar. 15, 2006 Page 223 of 556

REJ09B0026-0400

Examples of Buffer Operation: Figure 12.38 shows an operation example in which GRA has

been designated as an output compare register, and buffer operation has been designated for GRA

and GRC.

This is an example of TCNT operating as a periodic counter cleared by compare match B.

Pins FTIOA and FTIOB are set for toggle output by compare match A and B.

As buffer operation has been set, when compare match A occurs, the FTIOA pin performs toggle

outputs and the value in buffer register is simultaneously transferred to the general register. This

operation is repeated each time that compare match A occurs.

The timing to transfer data is shown in figure 12.39.

GRB

TCNT value

Counter is cleared by GBR compare match

Time

Compare match A

H'0250

H'0200

H'0100

H'0000

FTIOB

FTIOA

H'0200

H'0250

H'0200

H'0100

H'0200

GRC

H'0100

GRA

Figure 12.38 Example of Buffer Operation (1)

(Buffer Operation for Output Compare Register)

HD64F36034 Datasheet(PDF) 255 Page - Renesas Technology Corp