SH7124 datasheet(147/774 Pages) RENESAS

147 / 774 page

Section 7 User Break Controller (UBC)

Rev. 4.00 Jul. 25, 2008 Page 127 of 750

REJ09B0243-0400

7.2.11

Break Control Register (BRCR)

BRCR sets the following conditions:

1. Channels A and B are used in two independent channel conditions or under the sequential

condition.

2. A break is set before or after instruction execution.

3. Specify whether to include the number of execution times on channel B in comparison

conditions.

4. Determine whether to include data bus on channels A and B in comparison conditions.

5. Enable PC trace.

6. Specify whether to request the user break interrupt when channels A and B match with

comparison conditions.

BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for

setting a variety of break conditions.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

987654321

0000000000000000

RRRRRRRRRRRR

R/W

0000000000000000

R/W

----------

UBIDB

UBIDA

SCM

FCA

SCM

FCB

SCM

FDA

SCM

FDB

PCTE

PCBA

DBEA

PCBB

DBEB

SEQ

ETBE

Bit

Bit Name

Initial

Value

R/W

Description

31 to 20



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

UBIDB

R/W

User Break Disable B

Enables or disables the user break interrupt request

when the channel B break conditions are satisfied.

0: User break interrupt request is enabled when break

conditions are satisfied

1: User break interrupt request is disabled when break

conditions are satisfied

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