SH7124 datasheet(149/774 Pages) RENESAS

149 / 774 page

Section 7 User Break Controller (UBC)

Rev. 4.00 Jul. 25, 2008 Page 129 of 750

REJ09B0243-0400

Bit

Bit Name

Initial

Value

R/W

Description

SCMFDB

R/W

I Bus Cycle Condition Match Flag B

When the I bus cycle condition in the break conditions

set for channel B is satisfied, this flag is set to 1. In

order to clear this flag, write 0 into this bit.

0: The I bus cycle condition for channel B does not

match

1: The I bus cycle condition for channel B matches

PCTE

R/W

PC Trace Enable

0: Disables PC trace

1: Enables PC trace

PCBA

R/W

PC Break Select A

Selects the break timing of the instruction fetch cycle

for channel A as before or after instruction execution.

0: PC break of channel A is set before instruction

execution

1: PC break of channel A is set after instruction

execution

9, 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DBEA

R/W

Data Break Enable A

Selects whether or not the data bus condition is

included in the break condition of channel A.

0: No data bus condition is included in the condition of

channel A

1: The data bus condition is included in the condition of

channel A

PCBB

R/W

PC Break Select B

Selects the break timing of the instruction fetch cycle

for channel B as before or after instruction execution.

0: PC break of channel B is set before instruction

execution

1: PC break of channel B is set after instruction

execution

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