SH7124 datasheet(152/774 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 4.00 Jul. 25, 2008 Page 132 of 750

REJ09B0243-0400

7.2.13

Branch Source Register (BRSR)

BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source

instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0

by a power-on reset or manual reset when BRSR is read or the setting to enable PC trace is made.

Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue structure

and a stored register is shifted at every branch.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

987654321

0000

RRRRRRRRRRRRRRRR

----------------

RRRRRRRRRRRRRRRR

SVF

BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16

BSA15 BSA14 BSA13 BSA12 BSA11 BSA10

BSA9

BSA8

BSA7

BSA6

BSA5

BSA4

BSA3

BSA2

BSA1

BSA0

Bit

Bit Name

Initial

Value

R/W

Description

SVF

BRSR Valid Flag

Indicates whether the branch source address is stored.

This flag bit is set to 1 when a branch occurs. This flag

is cleared to 0 when BRSR is read, the setting to

enable PC trace is made, or BRSR is initialized by a

power-on reset.

0: The value of BRSR register is invalid

1: The value of BRSR register is valid

30 to 28



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

27 to 0

BSA27 to

BSA0

Undefined R

Branch Source Address

Store bits 27 to 0 of the branch source address.

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