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SH7108 Datasheet(PDF) 127 Page - Renesas Technology Corp |
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SH7108 Datasheet(HTML) 127 Page - Renesas Technology Corp |
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127 / 560 page  Section 7 Bus State Controller (BSC) BSC1000C_000020020700 Rev.1.00 Sep. 18, 2008 Page 93 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external circuitry. 7.1 Features The BSC has the following features: • Address space is divided into four spaces (supported only by the SH7109) ⎯ A maximum linear 2-Mbyte bus width for the on-chip ROM enabled mode and a maximum 4-Mbyte bus width for the on-chip ROM disabled mode, as for the CS0 space (8 bits) ⎯ Wait states can be inserted by software for each space ⎯ Wait state insertion with the WAIT pin in external memory space access ⎯ Outputs control signals for each space according to the type of memory connected • On-chip ROM and RAM interfaces ⎯ On-chip ROM and RAM access of 32 bits in 1 state |
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