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32186 Datasheet(PDF) 365 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 365 Page - Renesas Technology Corp |
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365 / 1032 page ![]() 10.3 TOP (Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10 10-69 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 b0 12 3456 78 9 10 11 12 13 14 b15 TOP7ENS TOP7M TOP6M TOP67ENS TOP67CKS 0 00 000 000 000 00 00 TOP6,7 Control Register (TOP67CR) <Address: H’0080 02AA> <Upon exiting reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0." 00 1 TOP7ENS 0: Result selected by TOP67ENS bit R W TOP7 enable source select bit 1: TOP6 output 2, 3 TOP7M 00: Single-shot output mode R W TOP7 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 4, 5 No function assigned. Fix to "0." 00 6, 7 TOP6M 00: Single-shot output mode R W TOP6 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 8 No function assigned. Fix to "0." 00 9–11 TOP67ENS 000: Does not select the enable source R W TOP6, TOP7 enable source select bit 001: Does not select the enable source 010: Does not select the enable source 011: Does not select the enable source 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 No function assigned. Fix to "0." 00 14, 15 TOP67CKS 00: Clock bus 0 R W TOP6, TOP7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes: • This register must always be accessed in halfwords. • Operation mode can only be set or changed while the counter is inactive. Clock bus Input event bus 3 2 1 0 clk en udf TOP 6 clk en udf TOP 7 S S S : Selector 3 2 1 0 S Note: • This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.4 Outline Diagram of TOP6, TOP7 Clock and Enable Inputs |
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