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10.4 TIO (Input/Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-92

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.4.2 Outline of Each Mode of TIO

Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected.

(1) Measure clear/free-run input modes

In measure clear/free-run input modes, the timer is used to measure a duration of time from when the

counter starts counting until when an external capture signal is entered.And also it is possible to generate

both an interrupt requested by underflow at the counter or execution of measurement operation and a DMA

transfer request (for only the TIO8 and TIO9) upon underflow of the counter.

After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro-

nously with the count clock. When a capture signal is entered from an external device, the counter value at

that point in time is written into a register called the “measure register.”

In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter

starts counting down again. The counter returns to H’FFFF upon underflow, from which it starts counting

down.Furthermore when it underflows goes back to H’FFFF and continues down counting.

In measure free-run input mode, the counter continues counting down even after capture. The counter

returns to H’FFFF upon underflow, from which it starts counting down again.

To stop the counter, disable count by writing to the enable bit in software.

(2) Noise processing input mode

In noise processing input mode, the timer is used to detect that the input signal remained in the same state

for over a predetermined time.

In noise processing input mode, a "H" or "L" level on external input activates the counter and if the input signal

remains in the same state for over a predetermined time before the counter underflows, the counter generates

an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the

counter underflows, the counter temporarily stops counting and at the next cycle when a valid-level signal is

entered again, the counter is reloaded with the value that " the reload register -1" and restarts counting.

The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit.

Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8

and TIO9) upon underflow of the counter.

(3) PWM output mode (without correction function)

In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.

When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial

values in the reload 0 and reload 1 registers, the counter is loaded with the value that “ the reload 0 register

-1” and starts counting down synchronously with the count clock at the next cycle.The next cycle after the

first time the counter underflows, it is loaded with the value that “ the reload 1 register -1” and continues

counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each

time an underflow occurs.The effective counter value is “reload 0 register set value +1” or “reload 1 register

set value +1.”

The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with

PWM output period).

The F/F output waveform in PWM output mode is inverted (F/F output level changes from "L" to "H" or vice

versa), when the counter starts counting and each time it underflows.

Furthermore, it is possible to generate an interrupt request at even-numbered occurrences of underflow after the

counter is enabled and a DMA transfer request (for only the TIO8 and TIO9) every time the counter underflows.

In addition PWM output mode of TIO does not have function of correction.

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