32186 datasheet(384/1032 Pages) RENESAS

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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-88

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively.

When the timer is enabled, the counter starts counting down and when it underflows after reaching the mini-

mum count, the counter is loaded with the content of " the reload register -1" and continues counting down.

However the timing for reloading is at the cycle after underflow.

H'FFFF

H'0000

H'E000

H'A000

H'E000

H'(E000-1)

H'FFFF

Data inverted

by underflow

Data inverted

by underflow

Data inverted by

enable

Count clock

Correction register

F/F output

TOP interrupt request

due to underflow

Enable bit

Reload register

Counter

Underflow

(first time)

Underflow

(second time)

Enabled

(by writing to the enable bit

or by external input)

Count down from the

counter's set value

Count down from the

reload register's

set value

Count down from the

reload register's

set value

(Unused)

(Note 2)

Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled.

Note 2: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

(Note 2)

(Note 1)

Figure 10.3.18 Typical Operation in TOP Continuous Output Mode

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