32186 datasheet(381/1032 Pages) RENESAS

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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-85

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected

H'FFFF

H'0000

H'9000+H'0008

H'F000

H'A000

H'F000

H'(F000+0008+1)

H'0008

Write to the

correction register

H'9000

Data inverted

by underflow

Data inverted

by underflow

Correction register

F/F output

TOP interrupt request

due to underflow

Enable bit

Note 1: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

Reload register

Counter

Count clock

Underflow

(first time)

Underflow

(second time)

Enabled

(by writing to the enable bit

or by external input)

Undefined

(Note 1)

In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respec-

tively. When the timer is enabled, the counter starts counting down and at the cycle after the first underflow,

the counter is loaded with the content of " the reload register -1" and continues counting down. In the

diagram below, the value H’0008 is written to the correction register when the counter has counted down to

H’9000. As a result of this correction, the counter has its count value increased to H’9008 and counts

(H’F000 + 1 + H’0008 + 1) after the first underflow before it stops.

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