32186 datasheet(377/1032 Pages) RENESAS

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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-81

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

H'FFFF

H'0000

H'FFF8

H'(FFF0+0014)

H'0004

H'FFF0

H'0014

H'FFF8

H'FFFF

H'(FFF8-1)

Data inverted

by enable

Data inverted

by underflow

Counter

Count clock

Correction register

F/F output

Enable bit

Reload register

Write to the

correction register

Enabled

(by writing to the enable bit

or by external input)

Undefined

value

Actual count after overflow

Overflow occurs

Undefined

TOP interrupt request

due to underflow

Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled.

Note 2: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

(Note 2)

(Note 1)

Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction

In the example below, the reload register is initially set to H’FFF8. When the timer starts, the value that " the

reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value

H’0014 is written to the correction register when the counter has counted down to H’FFF0. As a result of this

correction, the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request

is generated for an erroneous overflowed count.

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