32186 datasheet(375/1032 Pages) RENESAS

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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-79

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode When Count is Corrected

H'(8000 - 1)

H'FFFF

H'0000

H'8000

H'5000

H'5000 + H'4000

H'8000

H'FFFF

H'4000

Undefined

F/F output

TOP interrupt request

due to underflow

Count clock

Correction register

Enabled

(by writing to the enable bit

or by external input)

Enable bit

Reload register

Write to the

correction register

Undefined

value

Disabled

(by underflow)

Counter

(Note 1)

Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 7.

Note 2: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

(Note 2)

Data inverted

by enable

Data inverted

by underflow

In the example below, the reload register is initially set to H’8000. When the timer starts, the value that " the

reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value

H’4000 is written to the correction register when the counter has counted down to H’5000. As a result of this

correction, the count has been increased to H’9000, so that the counter counts a total of (H’8000 + 1 +

H’4000 + 1) before it stops.

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