32186 datasheet(373/1032 Pages) RENESAS

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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-77

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined,

and does not have to be specific.) When the timer starts, the value that " the reload register -1" is loaded into

the counter, letting it start counting. Thereafter, it continues counting down until it underflows after reaching the

minimum count.

H'FFFF

H'0000

H'A000

H'FFFF

H'(A000-1)

Count clock

Correction register

Enabled

(by writing to the enable bit

or by external input)

F/F output

Disabled

(by underflow)

(Unused)

TOP interrupt request

due to underflow

Enable bit

Starts counting down from

the reload register set value

Reload register

Data inverted

by enable

Counter

Data inverted

by underflow

Indeterminate

value

(Note 1)

(Note 2)

Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled.

Note 2: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

Figure 10.3.8 Typical Operation in TOP Single-shot Output Mode

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