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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-76

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)

(1) Outline of TOP single-shot output mode

In single-shot output mode, the timer generates a pulse in width of "reload register set value+1" only once

and then stops.

When the timer is enabled (by writing to the enable bit in software or by external input) after setting the

reload register, at the next cycle the counter is loaded with the content of " the reload register -1" and starts

counting synchronously with the count clock. The counter counts down and stops when it underflows after

reaching the minimum count.

The F/F output waveform in single-shot output mode is inverted (F/F output levels change from "L" to "H" or

vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of "reload

count value is "reload register set value + 1."

For example, if the initial reload register value is 7, then the count value is 8.

Figure 10.3.7 Example of Counting in TOP Single-shot Output Mode

123

456

H'FFFF

(Note 3)

Enable

Reload

Counter

Interrupt request

Underflow

Count value = 8

Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 7.

Note 2: A count clock dependent delay is included before F/F output changes state after the timer is enabled.

Note 3: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

F/F output

Count clock

(Note 2)

(Note 1)

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