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32186 Datasheet(PDF) 371 Page - Renesas Technology Corp

Part # 32186
Description  MCU
PDF  1032 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

32186 Datasheet(HTML) 371 Page - Renesas Technology Corp

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10.3 TOP (Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS
10
10-75
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
b0
12
3456
78
9
10
11
12
13
14
b15
TOP10 TOP9
TOP8
TOP7
TOP6
TOP5
TOP4
TOP3
TOP2
TOP1
TOP0
CEN
CEN
CEN
CEN
CEN
CEN
CEN
CEN
CEN
CEN
CEN
0
00
000
000
000
00
00
TOP0–10 Count Enable Register (TOPCEN)
<Address: H’0080 02FE>
<Upon exiting reset: H’0000>
b
Bit Name
Function
R
W
0–4
No function assigned. Fix to "0."
00
5
TOP10CEN (TOP10 count enable bit)
0: Stop counting
R
W
6
TOP9CEN (TOP9 count enable bit)
1: Enable counting
7
TOP8CEN (TOP8 count enable bit)
8
TOP7CEN (TOP7 count enable bit)
9
TOP6CEN (TOP6 count enable bit)
10
TOP5CEN (TOP5 count enable bit)
11
TOP4CEN (TOP4 count enable bit)
12
TOP3CEN (TOP3 count enable bit)
13
TOP2CEN (TOP2 count enable bit)
14
TOP1CEN (TOP1 count enable bit)
15
TOP0CEN (TOP0 count enable bit)
Note: • This register must always be accessed in halfwords.
The TOP0–10 Count Enable Register controls operation of TOP counters. To enable any TOP counter in
software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1." To
stop any TOP counter, enable its corresponding enable protect bit for write and reset the count enable bit by
writing "0."
In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable
bit is automatically reset to "0." Therefore, the TOP0-10 Count Enable Register when accessed for read serves
as a status register indicating whether the counter is operating or idle.
WR
bn
TOPm enable protect
(TOPmPRO)
WR
EN-ON
TOPm external enable
(TOPmEEN)
TINnS
TOPm count enable
(TOPmCEN)
TOP enable control
Input processing
selection
F/F
F/F
F/F
Event bus
TINn
Figure 10.3.6 Configuration of the TOP Enable Circuit



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