32186 datasheet(379/1032 Pages) RENESAS

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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-83

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respec-

tively. When the timer is enabled, the counter starts counting down and at the cycle after it underflows , the

counter is loaded with the content of " the reload register -1" and continues counting down. The counter

stops when it underflows second time.

Figure 10.3.13 Typical Operation in TOP Delayed Single-shot Output Mode

H'FFFF

H'0000

Underflow

(first time)

Count down from the

counter's set value

H'A000

Underflow

(second time)

H'F000

Count down from the

reload register's

set value

H'(F000-1)

(Unused)

H'FFFF

H'F000

Data inverted

by underflow

Data inverted

by underflow

Count clock

Correction register

Enabled

(by writing to the enable bit

or by external input)

F/F output

TOP interrupt request

due to underflow

Enable bit

Reload register

Counter

(Note 1)

Note 1: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

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