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10.3 TOP (Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-82

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function)

(1) Outline of TOP delayed single-shot output mode

In delayed single-shot output mode, the timer generates a pulse in width of "reload register set value + 1"

after a finite time equal to "counter set value + 1" only once and then stops.

When the timer is enabled (by writing to the enable bit in software or by external input) after setting the

counter and reload register, it starts counting down from the counter’s set value synchronously with the

count clock. At the cycle after the first time the counter underflows, it is loaded with the value that " the

reload register -1" and continues counting down. The counter stops when it underflows next time.

The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H"

or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width

of "reload register set value + 1" after a finite time equal to "first set value of counter + 1" only once.

An interrupt request can be generated when the counter underflows first time and next.

The "counter set value + 1" and "reload register set value + 1" are effective as count values.

For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates

as shown below.

Figure 10.3.12 Example of Counting in TOP Delayed Single-shot Output Mode

123

678

H'FFFF

F/F output

(Note 1)

Count clock

dependent delay

Enable

Reload

Counter

Interrupt request

Count clock

Underflow

Count value = (4 + 1) + (5 + 1) = 11

(Note 2)

Note 1: What actually is seen in the cycle immediately during underflow is H'FFFF(underflow value), and not 5.

Note 2: The value that "reload register - 1" is reloaded.

Note: • This diagram does not show detailed timing information.

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