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10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-180

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.8.15 Operation in TOU Single-shot PWM Output Mode (without Correction Function)

(1) Outline of TOU single-shot PWM output mode

In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given

duty cycle only once. When PWM output mode, it is operated as a 16 bit timer.

When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is

loaded with the value that " the reload 0 register -1" and starts counting down synchronously with the count

clock at the next cycle. At the cycle after the first time the counter underflows, it is loaded with tthe value that

" the reload 1 register -1" and continues counting. The counter stops when it underflows next time. The "

reload 0 register set value + 1" and " reload 1 register set value + 1" respectively are effective as count

values.

The timer can be stopped in software, in which case it stops at the same time count is disabled by writing to

the enable bit (and not in synchronism with PWM output period).

The F/F output waveform in single-shot PWM output mode is inverted (F/F output level changes from "L" to

"H" or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output is not

inverted when the counter is enabled.) An interrupt request and DMA transfer request can be generated

when the counter underflows second time after being enabled.

If the value ‘H'FFFF’ is set in either the reload 0 register or the reload 1 register, F/F output will not be

inverted although an interrupt request is generated upon underflow, making it possible to produce a 0% or

100% duty-cycle PWM output. Because a 0% or 100% duty-cycle needs to be determined when reloading

the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA

transfer request is generated. However, startup requests to other timers are not delayed. For details, see

Section 10.8.19, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output

Modes.”

Note that TOU’s single-shot PWM output mode does not have the count correction function.

(2) Precautions about using TOU single-shot PWM output mode

The following describes precautions to be observed when using TOU single-shot PWM output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the

enable bit, the latter has priority so that count is disabled.

• If the counter is accessed for read at the cycle of underflow, the counter value is read out as H'FFFF but

changes to “reload register value -1” at the next count clock timing.

• Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting

at present. Updating is reflected at the next PWM period after updating reload 0 register.

Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count

clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. How-

ever, startup requests to other timers are not delayed. For details, see Section 10.8.19, “0% or 100% Duty-

Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.”

32186 Datasheet(PDF) 476 Page - Renesas Technology Corp