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32186 Datasheet(PDF) 480 Page - Renesas Technology Corp

Part # 32186
Description  MCU
PDF  1032 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

32186 Datasheet(HTML) 480 Page - Renesas Technology Corp

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10.8 TOU (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS
10
10-184
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
10.8.17 Operation in TOU Single-shot Output Mode (without Correction Function)
(1) Outline of TOU single-shot output mode
In single-shot output mode, the timer generates a pulse in width of " reload register set value + 1" only once
and then stops.
When the timer is enabled after setting the reload register, the counter is loaded with the content of " the
reload register -1" and starts counting synchronously with the count clock at the next cycle. The counter
counts down and stops when it underflows after reaching the minimum count.
The F/F output waveform in single-shot output mode is inverted (F/F output levels change from "L" to "H" or
vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of " reload
register set value + 1" only once.
An interrupt request and DMA request can be generated when the counter underflows.
The count value is " reload register set value + 1." (For counting operation, see also Section 10.3.9, “Opera-
tion of TOP Single-shot Output Mode.”)
(2) Precautions about using TOU single-shot output mode
The following describes precautions to be observed when using TOU single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the
enable bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay
is generated before F/F output is inverted after writing the enable bit.



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