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10.8 TOU (Output-Related 24-Bit Timer)

MULTIJUNCTION TIMERS

10-186

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.8.18 Operation in TOU Continuous Output Mode (without Correction Function)

(1) Outline of TOU continuous output mode

In continuous output mode, the timer counts down starting from the set value of the counter and when the

counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each

time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of "

reload register set value + 1."

When the timer is enabled after setting the counter and reload register, it starts counting down from the

counter’s set value synchronously with the count clock and when the minimum count is reached, generates

an underflow. At the next cycle after this underflow causes the counter to be loaded with the content of " the

reload register -1" and start counting over again. Thereafter, this operation is repeated each time an under-

flow occurs. To stop the counter, disable count by writing to the enable bit in software.

The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or

vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer

stops counting. An interrupt request and DMA request can be generated each time the counter underflows.

The " counter set value + 1" and " reload register set value + 1" are effective as count values. (For counting

operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”)

(2) Precautions about using TOU continuous output mode

The following describes precautions to be observed when using TOU continuous output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the

enable bit, the latter has priority so that count is disabled.

• If the counter is accessed for read at the cycle of underflow, the counter value is read out as H'FFFF but

changes to “ reload register value -1” at the next count clock timing.

• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay

is generated before F/F output is inverted after writing the enable bit.

32186 Datasheet(PDF) 482 Page - Renesas Technology Corp